1. Field of the Invention
The present invention relates generally to the field of integrated frequency synthesizers and oscillators. Specifically, the present invention relates to the field of variable voltage oscillators implemented using low voltage digital CMOS processes.
2. Description of the Related Art
High speed Phase Locked Loops are used in modern communication systems for many purposes, including frequency synthesizing operations such as clock generation, data recovery, and retiming. Such frequency synthesizers are typically analog circuits, but to lower cost a trend in industry is to implement such circuits using low voltage digital CMOS processes.
Frequency synthesizers are typically voltage controlled, and thus suffer from signal headroom and scalability problems when implemented in low voltage digital CMOS processes. In spite of these problems, use of advanced submicron digital CMOS processes to implement analog clock generation and recovery continues to increase due to its benefit of significantly lower operating voltages.
As operating voltages are reduced, however, the amount of voltage range, or voltage headroom, available for these analog circuits is significantly reduced. As a result, the voltage range available for a frequency control and correction signal is greatly reduced requiring that the oscillator function within more rigid design parameters. Thus, this decreased headroom for analog circuits imposes a significant constraint on circuit design in high frequency clock synthesis.
Although, the corollary to this trend is the availability of complex digital functions in minimal area, it is well known that the integration of complex high speed digital functions in close proximity to low headroom, high gain analog clock components gives rise to spurious frequencies and higher jitter components.
Thus, a need exists for a method of implementing analog circuits within a low voltage digital CMOS process with reduced jitter and expanded voltage headroom.